Integrated Circuits for Analog Signal Processing by Esteban Tlelo-Cuautle

Author:Esteban Tlelo-Cuautle
Language: eng
Format: epub
Publisher: Springer New York, New York, NY

8.5 A Comparator in 0.12 μm CMOS Technology Requiring 0.5 V at 600 MHz

This section describes a comparator, which is capable to work down to a supply voltage of 0.5 V with a maximum clock frequency of 600 MHz [21]. Figure 8.7 shows the schematic of the comparator. Like in many comparator circuits, here a clock cycle is divided into a reset and a comparison phase. During reset phase the voltage level at CLK is V SS thus turning off transisitors N0 and N1 and turning on transistors P0 and P1. In reset phase nodes CLK and CLKR have the same level of V SS because the gate-source voltage of N8 is larger than the threshold voltage V tN8 of this transistor. Both output nodes OUT and are pulled to potential V Comp thus creating an initial condition for the following comparison phase. Comparison of the input voltages CINP with CINN starts when CLK switches to voltage level V Comp In opposite to a conventional comparator, transistors P0 and P1 are used to reset the comparator when CLK has the level of V SS and when CLK changes to level V Comp the same transistors are biased as active load. So additional reset switches, which contribute parasitic capacitances to the output nodes and reduce speed are avoided. Because transistor N8, which is biased with an adjustable bias voltage TBIAS at its gate, has been added to the clock line, CLKR rises to TBIAS − V tN8, if sub-threshold and leakage currents are neglected for simplicity and an ideal quadratic MOS-transistor characteristic is assumed. So P0 and P1 are biased to become active loads. At the beginning of the comparison phase the output nodes have been pre-charged initially to V Comp from previous reset. Transistors N6 and N7 are on and each of the transistors N2 and N3 (latch) has initially a gate voltage near V Comp . Therefore the tendency to speed up transistors N2 and N3 is given. This and the fact that N2 to N8 are transistors with a low threshold voltage of about 0.29 V, provided by this CMOS process, it is possible to drive the comparator even down to a supply voltage of V Comp  = 0. 5 V. Due to positive feedback of transistors N2 and N3 the latch regenerates depending on the input-voltage difference at transistors N4 and N5. Transistors N6 and N7 are added below the input transistors N4 and N5 to reduce static current flow after the decision of the comparator. This can be seen when the voltage level at e.g. OUT is below the threshold voltage of N7, the path via N5 and N0 to V SS is cut off. Also the path between OUT and via transistors N4, N5, N6 and N7 is cut off. At pin NWELL the separated n-well of P0 and P1 can be biased with a DC voltage to somewhat utilize the backgate effect to have an additional possibility to adjust the currents through transistors P0 and P1. Transient simulations of the comparator can be seen in Fig.

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